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The temporary score has been published, please contact with TA or me ASAP if you have any problem.

Syllabus

9/14 9/21	Introduction [PDF] [Print Version] Why and What is this course ? What is a computer ? Digital Binary Systems READING: Chap. 1
9/21 10/5	Two-Level Combinational Logic [PDF] [Print Version] Logic Functions Gate Logic Two-Level Simplification READING: B.2, B.3 Homework #1 [PDF], deadline = 10/12
9/28	HOLIDAY
10/12 10/19 10/26	Instructions: Language of the Computer [PDF] [Print Version] Operations and Operands of the Computer Hardware Representing Instructions in the Computer Logical Operations Instructions for Making Decisions Supporting Procedures in Computer Hardware Communicating with People MIPS Addressing for 32-Bit Immediates and Addresses Translating and Starting a Program Arrays versus Pointers READING: Chap. 2 w/o 2.11~14, A.10 Homework #2 [PDF], deadline = 11/2 NOTE: the 6th problem has been canceled.
10/26 11/2	Arithmetic for Computers [PDF] [Print Version] Signed and Unsigned Numbers Addition and Subtraction Constructing a Basic Arithmetic Logic Unit Multiplication and Division Floating Point READING: Chap. 3, B.5 Homework #3 [PDF], deadline = 11/9
11/9	Assessing and Understanding Performance [PDF] [Print Version] CPU Performance and Its Factors Measuring Performance READING: Chap. 4
11/16	mid-term exam. range: the materials until 11/9
11/23 11/30 12/7	The Processor: Datapath and Control [PDF] [Print Version] Memory Elements Building a Datapath A Simple Implementation Scheme Finite State Machines A Multicycle Scheme Exceptions Microprogramming READING: Chap. 5 w/o 5.8, B.7, B.8, B.10 NOTE: the class of 12/7 will be started from 09:30. Homework #4 [PDF], deadline = 12/14
12/14 12/21 12/28	Enhancing Performance with Pipelining [PDF] [Print Version] An Overview of Pipelining A Pipelined Datapath Pipelined Control Data Hazards and Forwarding Data Hazards and Stalls Branch Hazards READING: Chap. 6 w/o 6.7~9 Homework #5 [PDF], deadline = 1/4
12/28 1/4	Exploiting Memory Hierarchy [PDF] [Print Version] The Basic of Caches Measuring and Improving Cache Performance Virtual Memory A Common Framework for Memory Hierarchies READING: Chap. 7 w/o 7.4 (virtual memory)
1/11	final exam. range: the materials until 1/4

Textbook

• David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 3rd. ed. , Morgan Kaufmann, 2004.

Reference

• David A. Patterson and John L. Hennessy. Computer Architecture: A Quantitative Approach, ISE, 3rd ed. , Morgan Kaufmann, 2002.
  
• Randy H. Katz. Contemporary Logic Design , The Benjamin/Cummings Publishing, 1993.
  
• John P. Hayes. Introduction to Digital Logic Design, 2nd ed., Addison-Wesley, 1996.

Grade Measurement

Homework (maybe five or six times) + Examinations (twice) + Participants

Pre-courses

Logic Design (Introduction to Computer)